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ANSYS achieves certification for TSMC’s 3D chip stacking technology

TSMC certified ANSYS solutions for its innovative System-on-Integrated-Chips (TSMC-SoIC) advanced 3D chip stacking technology. SoIC is an advanced interconnect technology for multi-die stacking on system-level integration using Through Silicon Via (TSV) and chip-on-wafer bonding process — enabling customers with greater power efficiency and performance for highly complex and demanding cloud and data centre applications.

ANSYS multiphysics solutions for SoIC enable multi-die co-simulation and co-analysis for extraction, power and signal integrity analysis, power and signal electromigration analysis, and thermal and thermal-induced stress analysis.

In addition to SoIC certification, TSMC validated the reference flow for the latest Chip-on-Wafer-on-Substrate (CoWoS) packaging technology using ANSYS RedHawk, ANSYS RedHawk-CTA, ANSYS CMA and ANSYS CSM and their corresponding chip models for system level analysis.

‘We're pleased with the result of our collaboration with ANSYS in delivery of TSMC-SoIC technology reference flow, which empowers customers to address growing performance, reliability and power demands for cloud and data centre applications,’ said Suk Lee, senior director, design infrastructure management division at TSMC. ‘The collaborative efforts combining ANSYS' comprehensive chip-package co-analysis solutions with TSMC SoIC advanced chip stacking technology address complex multiphysics challenges in 3D-IC packaging technologies.’

‘Our 3D-IC solutions address complex multiphysics challenges to meet the stringent power, performance, thermal and reliability requirements,’ said John Lee, general manager at ANSYS. ‘ANSYS' comprehensive chip aware system and system aware chip signoff solutions empower mutual customers to accelerate design convergence with greater confidence.’


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