Imec launches university consortium around next generation of chips
Imec launches a first-of-its-kind European university consortium on CMOS 2.0, bringing together 26 university groups to research chip technologies beyond traditional transistor scaling.
Credit: imec
CMOS 2.0 rethinks how future chips are designed, using 3D wafer stacking and heterogeneous integration to enable more energy‑efficient and powerful computing systems.
Register for FREE to keep reading
Join 12,000+ scientists, engineers, and IT professionals driving innovation through informatics, HPC, and simulation with:
- Insights into HPC, AI, lab informatics & data
- Curated content for life sciences, engineering & academia
- Access to Breakthroughs: real-world computing success
- Free reports & panels, including the Lab Informatics Guide
- White Papers & software updates for smarter research
Sign up now
Already a member? Log in here
Your data is protected under our privacy policy.
