Four of the top 10 supercomputers on the latest TOP500 list run on AMD silicon – a remarkable turnaround for a company that, little more than a decade ago, was fighting to stay relevant in the CPU market. Mark Papermaster, AMD's Chief Technology Officer and Executive Vice-President, has spent the past 15 years driving the strategy behind that resurgence.
In this interview, Papermaster traces the architectural bets that redefined AMD's trajectory: the ground-up rebuild of its CPU line with the ‘Zen’ family, the parallel push for leadership GPUs, and the modular Infinity Architecture that ties them together. That early commitment to chiplet technology – now a high-volume approach across the industry – has let AMD tailor hardware to increasingly specialised workloads, from agentic AI to the highest-FP64-precision computing science demands. He tells Scientific Computing World about the move to two-nanometre manufacturing with EPYC Venice, the memory-bandwidth pressures of inferencing and agentic AI, and how AMD is positioning its hardware and software roadmap to shape scientific discovery and AI over the next decade.
Can you tell me about your role at AMD?
Mark Papermaster: For most of the last 15 years, I've had two roles, CTO and head of what's called Technology and Engineering, driving the bulk of R&D across the company. That was important in the formative years of remaking AMD into such a force in HPC. It was important to have one leader setting the technology direction while driving a very rigorous execution and culture of innovation and collaboration across the company, and that served us well. For the past year or so, I've been focused primarily on the CTO role.
That role continues to drive the company's technical direction; we do so very rigorously, and I've been doing it for 15 years. We look at where technology and applications are going. Fifteen years ago was the dawn of AI, and really the dawn of heterogeneous computing, CPUs and GPUs, and how you bring those together to move the state of the art of computation forward. Back then, it was really just the domain of huge labs and sovereign labs across various organisations, but as AI and AI for science have gained momentum, you now see massive, heterogeneous compute clusters – CPUs alongside various bespoke accelerators, GPUs, and other bespoke accelerators – commonplace across the world. That's a great example of the CTO's role: anticipating these trends and positioning our product roadmap and portfolio to be front and centre, because that's what AMD needs to be: a provider of preeminent computing technology for the industry at large.
Which architectural decision has had the greatest impact on that resurgence, particularly in HPC and the data centre in general?
MP: There was a twofold decision we made years ago when Lisa Su and I were recruited to AMD – to focus on providing the best high performance, to differentiate AMD on that basis. That led to some very important decisions, starting with the CPU – scrapping the prior CPU efforts in place and creating a new CPU family targeted to be leadership from its very inception, followed by investment to have a leadership GPU too.
That upfront decision to invest in heterogeneous computing drove a number of phenomenally important architectural decisions. Alongside starting the new compute engine efforts, we simultaneously made the decision to create what we call Infinity Fabric, which let us invest in a modular approach that enabled not just heterogeneous compute cores, but also flexibility in how we partitioned into what became a chiplet approach. AMD led the industry in investing in a high-volume chiplet approach to computing, and that flexibility was extremely instrumental in winning bids for the largest supercomputers launched over the last five or six years.
It all traces back to that decision [in three ways]. One, invest in leadership compute engines, CPU and GPU. Two, enable that with a modular approach to how they're stitched together. Three, invest in chiplet technology to leverage that modularity, so you can mix and match and create different configurations for different compute needs. That's what we saw coming – there wouldn't be a vanilla need for computing, but workloads would need specialised configurations to operate most efficiently. That's exactly how the industry has played out, and we called that over a decade ago.
What about EPYC Venice and the move to 2nm? What new capabilities does this enable for scientific computing?
MP: The 6th-gen Epyc is really a statement of our continued commitment to leadership. The Zen 6 core, the new generation of the core, brings significant improvements in instructions per clock. We'd already invested in a native 512-bit-wide vector engine, AVX-512–native, and we're making it more robust now by bringing even more memory bandwidth to those cores. We bump up to PCIe Gen 6, which provides more I/O bandwidth, and we also bump up to CXL 3.1, giving system providers yet more options for bringing peripheral devices on board and extending memory.
Two-nanometre manufacturing gives us two things. Firstly, more performance per watt in every CPU core. For our high-performance versions, we didn't sacrifice the ability to ramp up to high frequency. We are a leader with what we call 3D V-Cache, which lets you stack SRAM; that combination lets us deliver high frequency, high performance, and much larger local caching.
With the two-nanometre node, you also get density. For agentic workloads, we have another version with a higher density of cores, up to 256 CPU cores on a single EPYC socket, which is ideal for agentic workflows needing massive throughput, because the CPU's role isn't just as a head node running a high-performance Venice CPU; it's also the orchestrator, the brain running all the analysis of context windows across broad AI operations.
How does the rise in agentic AI impact your architectural decision-making? Is memory bandwidth going to remain a bottleneck?
MP: Inferencing is indeed memory-bandwidth dependent, and that very much influenced our decisions on Venice. One was more memory options – you can run DDR or MRDIMM, which can run at very high bandwidth with the registered DIMM approach. We also have a variant called Verano with LPDDR. What you're seeing in the current era is not just the need for heterogeneous engines, different CPU and GPU configurations, different CPU core counts, but also different memory needs. With the flexibility we have, and very high volume, our market share on EPYC is now rapidly approaching 50%.
We have scale, and with that scale we can really give customers options. Leveraging our chiplet approach, we've added more variants to address unique needs across HPC, head-node applications for large AI clusters, and agentic clusters, which require super-high-density throughput and very high memory bandwidth.
Interconnect is always extremely important for us because we're focused on high performance. If you're providing the leading high-performance solutions in the industry, you have to, as I've always put it, ‘feed the beast’. You can't grow your compute engines without equally growing your connectivity to memory and I/O, and the ability to give customers configurability.
You saw that historically with AMD; look at what we did in late 2023 through 2024 with the MI300 family. We offered the MI300X, a beast for AI inference, and the MI300A, the HPC option, which integrated Zen CPUs with the Instinct GPU. That's the processor in the Lawrence Livermore supercomputer today – a top-five supercomputer; I think it's number two, having been number one for a number of years – as well as a number of installations across the world, including LUMI, HLRS in Germany, and other UK and European installations. It's been a huge stalwart of HPC implementations across Europe. We have our MI455 in the Helios rack we've announced, shipping next quarter in volume, followed by another variant called the MI430 that brings in a chiplet change optimised for HPC. On all of these, interconnect plays a huge role, because we require every variant we build to be optimised for the memory and I/O of its targeted market.
How will the chiplet design continue to evolve? Do you see demand for more specialised chiplets?
MP: I do, because the need for incredible efficiency in HPC and AI is driving what used to be a specialised need of HPC more broadly. There's now mass demand for HPC, and AI for science requires ever greater efficiency.
One way to achieve that efficiency is to tailor hardware computation to the algorithms required for a specific set of applications. So what you're seeing now is unique configurations required for agentic AI throughput, unique configurations for building up AI training and very-large-language-model inferencing at a head node with a GPU or accelerator cluster, and unique configurations required by sovereign nations and HPC labs for AI for science.
Is it a strategic decision to focus on FP64 and double precision in your GPUs?
MP: It is indeed strategic for AMD. We made a commitment to the HPC and AI-for-science market when we launched the MI300A back in 2024. The way we've been able to [continue that support] is by leveraging our modular approach to generate a version of our GPU that supports FP64 by swapping out a single chiplet, while keeping the rest of the infrastructure the same as in the much higher-volume AI market, which doesn't require that highest precision.
The very underpinnings of how we architected our implementation gave us the flexibility to support the HPC and AI-for-science market with native, high-precision FP64 in a way our competitors couldn't match without a much more significant investment.
When you're accelerating discovery, trying to crack how to solve fusion, doing new molecular studies, or modelling the atmosphere and weather more accurately, that all requires high precision, native FP64, the highest double-precision floating point. You can't get there with AI approximations alone.
The most efficient way to handle all those unique configurations for bespoke applications is a chiplet approach, tailoring the engines, the I/O and memory configuration, and the very math formats you support, to more efficiently serve the algorithms at hand for a given market, and we're incredibly well poised to do that with unique chiplets. What's also moving very rapidly is the technology to stitch those chiplets together even more efficiently.
Mark Papermaster is the Chief Technology Officer and SVP at AMD.
