Cadence/ARM test chip collaboration has legs
ARM and Cadence have announced details behind their collaboration to implement the first ARM Cortex-A57 processor on TSMC’s 16-nanometer FinFET manufacturing process.
The test chip was implemented using the complete Cadence RTL-to-signoff flow, Cadence Virtuoso custom design platform, ARM Artisan standard cell libraries and TSMC’s memory macros.
The Cortex-A57 processor is ARM’s highest-performing processor to-date and is based on the new ARMv8 architecture designed for computing, networking and mobile applications that require high performance at a low-power budget.
TSMC’s 16nmFinFET technology is described as a significant breakthrough that enables continued scaling of process technology to feature sizes below 20nm. This test chip, developed with Cadence’s custom, digital and signoff solutions for FinFET process technology, was a collaboration that resulted in several innovations and co-optimisations between manufacturing process, design IP, and design tools.
'More than ever, success at the leading edge of innovation requires deep collaboration. When designing SoCs incorporating advanced processors, like the Cortex-A57, and optimising the implementation using physical IP created for FinFET processes, the expertise of our partners is needed,' said Tom Cronk, executive vice president and general manager of the processor division at ARM.
'Our joint innovations will enable our customers to accelerate their product development cycles and take advantage of leading-edge processes and IP.'