PRACE

PRACE “Best Practice Guide - Modern Accelerators

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Hardware accelerators offer certain advantages over general-purpose Central Processing Units (CPUs) as they provide a greater computational throughput when applications exhibit high degrees of data parallelism, due to their highly parallel architectural design and high-bandwidth memory systems. These specialized chips are usually more energy-efficient, i.e. are capable of delivering much higher compute performance as compared to CPUs at the same power cost. These characteristics make accelerator technologies appealing both for system vendors and users.

PRACE “Best Practice Guide - Modern Processors”

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Processor manufacturers are continuously pushing the performance limits for delivering more computational capabilities to the end users. These efforts, however, typically imply new architectural modifications requiring corresponding guidance for the efficient utilization of the underlying platform by application developers.

FUTURE HPC TECHNOLOGIES

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The current technologies used for HPC systems will not be able to sustain the performance increase requested by the HPC/HPDA/AI 1 application communities. Since the end of the Dennard scaling and with the approaching end of the Moore’s law, the standard CMOS 2 technology has to be complemented by other approaches if we want to continue to deliver more performance. The three main HPC ecosystems beside Europe, namely US, China and Japan have undertaken significant research initiatives to work on these new approaches.

Application porting and code-optimization activities for European HPC systems

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Currently, the HPC community is actively working towards the development of next-generation HPC systems capable of delivering ExaFLOP performance. While these new HPC architectures open exciting opportunities to the computational scientific community, they also pose numerous challenges. Get interesting insights about current major large-scale application porting and code-optimization activities in Europe.

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