EDA Simulator Link continuous verification workflow

The MathWorks has released a continuous verification workflow that connects system-level models and algorithms developed in MATLAB and Simulink with digital hardware simulators from the three major EDA companies.

With the availability of EDA Simulator Link DS, which supports co-simulation between MATLAB and Simulink and the Synopsys VCS MX functional verification solution, The MathWorks completes its EDA Simulator Link portfolio, which also includes EDA Simulator Link MQ (for Mentor Graphics’ ModelSim and Questa) and EDA Simulator Link IN (for Cadence Incisive Simulator).

EDA Simulator Link products from The MathWorks offer support for VHDL, Verilog and mixed-language simulators, enabling engineers to connect MATLAB and Simulink to their choice of hardware description language (HDL) and register transfer level (RTL) simulator for their hardware design and verification tasks. The products also work seamlessly with Simulink HDL Coder from The MathWorks to automate integration of legacy RTL IP with designs developed in MATLAB and Simulink. The EDA Simulator Link products support design teams across FPGA and ASIC markets that are striving to reduce development time, design flaws and verification costs.

The previous EDA Simulator Link products in improving product quality and cutting verification time has fuelled demand for additional interfaces to hardware workflows. As a result, the EDA Simulator Link portfolio has expanded and has prompted EDA vendors to deliver similar tools for analog and mixed-signal simulators such as Synopsys Discovery AMS and Saber, Cadence Virtuoso Multi-Mode Simulation, Cadence PSpice and Cadence Allegro AMS Simulator and Mentor Graphics ADVance MS (ADMS).


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