The Mont-Blanc project which aims to define and build a new HPC architecture for exascale-class computing based on ARM technology has selected Cavium’s ThunderX2 ARM server processor to power its new high performance computing (HPC) prototype.
‘As the race to exascale intensifies, we are pleased to be the vendor of choice to partner with Atos to deliver Mont-Blanc platform’ said Rishi Chugh, director of marketing, data center processor group at Cavium. ‘ThunderX2 builds on established architecture and ecosystem of ThunderX delivering performance competitive with next generation of incumbent processors.’
Since the Mont-Blanc project was first started in 2011 the goals have been to design a new architecture for HPC around compute and energy efficiency of exascale systems. The plan is to use energy efficient devices processors used in embedded and mobile devices – ARM processors, which are much more efficient than standard Intel CPUs.
The project takes a holistic approach, encompassing not just hardware, but also operating system and tools, and applications. This new platform will continue this trend allowing the Mont-Blanc partners, to assess options for maximum compute efficiency – and to further develop the software ecosystem for ARM HPC platforms and to implement life-size tests.
The ThunderX2 product family is Cavium’s 2nd-generation 64-bit ARMv8-A server processor SoCs for high-performance computing in the data centre and cloud applications. With fully out of order high-performance custom cores supporting single and dual socket configurations, ThunderX2 is optimised to drive computational performance, delivering high memory bandwidth and memory capacity. The ThunderX2 processor family is fully compliant with ARMv8-A architecture specifications as well as ARM’s SBSA and SBBR standards and is widely supported by industry leading OS, Hypervisor and SW tool and application vendors.
The new Mont-Blanc prototype will be built by Atos, the coordinator of phase 3 of Mont-Blanc, using its Bull expertise and products. The platform will leverage the infrastructure of the Bull sequana pre-exascale supercomputer range for network, management, cooling, and power.
‘ThunderX2 is a server-class chip designed for high compute performance. With the adoption of this new generation of power- and performance-efficient processors, we are entering a new and exciting dimension of the Mont-Blanc project. This already gives us a glimpse of what a European exascale-class HPC platform could be in the near future,’ said Etienne Walter, coordinator of phase 3 of the Mont-Blanc project.