DARPA announces research on next generation processing technology
DARPA (Defense Advanced Research Projects Agency) has announced the academic and industry research groupsselected to develop new computing technologies to drive computing performance post Moore’s Law.
At the Electronics Resurgence Initiative (ERI) Summit, held last week in San Francisco, DARPA announced research teams that will work on multiple projects under three main themes: reconfigurable hardware; modern System-on-Chip (SoC) designs; and novel materials and approaches to circuit integration.
ERI is a five-year, $1.5 billion investment to jumpstart innovation in the electronics industry. The project has been setup to address the challenges that face the microelectronics industry. Partly though subsidising the research and development and also by encouragement the US government can use this DARPA initiative to nurture research in systems architectures, advanced new materials, and circuit design tools through a mix emerging programs.
The reconfigurable computing technology research focuses on two key areas; Software Defined Hardware (SDH) and Domain-specific System on Chip (DSSoC).
The SDH and DSSoC programs seek to explore new ways to co-optimise software and hardware without requiring more complex programming. Both programs aim to bridge the gap between the efficiency of custom hardware such as application specific integrated circuits (ASICs) and the flexibility provided by more general purpose computing hardware.
The SDH programme will feature input from Intel, NVIDIA, Qualcomm, Systems & Technology Research (STR), Georgia Institute of Technology, Stanford University, University of Michigan, University of Washington, and Princeton University. Under the Domain-specific System on Chip (DSSoC) program, the research teams include IBM, Oak Ridge National Labs, Arizona State University, and Stanford University.
The second research area focuses on SoC design complexity and cost barriers. The goal is to create an environment that could catalyse the next wave of US semiconductor innovation and broaden the competitive field for circuit design.
The ERI has designed two programmes that will address these issues – the Intelligent Design of Electronic Assets (IDEA) program and the Posh Open Source Hardware (POSH) program which feature input from the University of California, San Diego; Northrop Grumman Mission Systems; Cadence Design Systems; Xilinx; Synopsys; University of Southern California; Princeton University; and Sandia National Laboratories.
The two programmes will help DARPA to answer one of the fundamental questions of processor design ‘Can we dramatically lower the barriers to modern System-on-Chip design and unleash a new era of circuit and system specialisation and innovation?’ In doing so DARPA and the US companies and research institutes involved in the projects would help to revolutionise the development of SoC’s by largely automating the design process.
Through the creation of a software-based, completely automated physical layout generator and an open-source intellectual property (IP) ecosystem, the IDEA and POSH programs aim to create a ‘no human in the loop’ layout generator that would enable users to complete the physical design of electronic hardware within 24 hours.
‘Through the IDEA program, DARPA aims to eliminate the DoD's resource and expertise gap associated with custom electronic hardware design for the most advanced technologies by enabling full automation and applying machine intelligence,’ said Andreas Olofsson, the Microsystems Technology Office program manager leading IDEA and POSH.
Overcoming Moore’s Law
Perhaps most relevant of these projects to the HPC industry is the Materials & Integration research area which DARPA has organised into two programs – the Three Dimensional Monolithic System-on-a-Chip (3DSoC) program and the Foundations Required for Novel Compute (FRANC) program.
At the ERI summit Darpa announced that the Georgia Institute of Technology, Stanford University, Massachusetts Institute of Technology, and Skywater Technology Foundry will be working under the 3DSoC program. HRL Laboratories; Applied Materials, Ferric, University of California, University of Minnesota, and University of Illinois at Urbana-Champaign have been selected for the FRANC programme.
These projects hope to overcome one of the fundamental performance bottlenecks facing HPC users the ‘memory bottleneck’. By setting researchers the task of investigating vertical, rather than flat or planar integration of microsystem components—as well as new materials, components, and algorithms capable of closing the gap between memory and logic functions—the program managers leading the 3DSoC and FRANC programs hope to create new means of computing vast amounts of information.
Today, electronic system performance is limited by the time and power required to access system memory. Integrating memory and logic into a single, monolithic 3D SoC stack has the potential to significantly reduce this constraint.
The 3DSoC program aims to develop materials, design tools, and fabrication techniques for building microsystems on a single substrate with a third dimension. To achieve the program’s goals, 3DSoC research teams aim to integrate logic, memory, and input/output (I/O) elements in ways that dramatically shorten—more than 50-fold—computation times while using less power.
‘Under the 3DSoC program, the researchers will build on a decade’s worth of theory and academic demonstration to integrate processes into a widely available foundry that should help, in practice, unleash these technologies in the field of microelectronics,’ said Linton Salmon, the Microsystems Technology Office program manager leading 3DSoC.
To help further address the ‘memory bottleneck’ the second Materials & Integration programme will explore alternatives to the conventional separation of memory and logic functions – non von Neumann based architectural designs.