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NICS announces strategic engagement with Intel

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The University of Tennessee's National Institute for Computational Sciences (NICS) has entered a multi-year strategic engagement with Intel to pursue development of next-generation HPC solutions based on the Intel MIC architecture and the design of scientific applications emphasising a sustainable approach for both performance and productivity.

Funded by the National Science Foundation (NSF) and located at Oak Ridge National Laboratory, NICS manages the Cray XT5 Kraken, the NSF’s most productive supercomputer.

'As a leading centre for high-performance computing, NICS is working with Intel to ensure that the Intel MIC architecture and its software environment are developed to meet the needs of the scientific supercomputing community,' explained Glenn Brook, director of the Application Acceleration Center of Excellence and head of the Intel MIC architecture initiative at NICS.

'Intel is pleased to work closely with NICS to help move highly parallel scientific codes from multi-core to many core technology,' said Raj Hazra, general manager of the Technical Computing Group at Intel Corporation. 'Our partnership with NICS seeks to help scientists reduce application development time with the benefit of faster time to results and insight.'

Next-generation systems based on the Intel MIC architecture will combine multi-core Intel Xeon processors with Intel MIC co-processors. Such systems are expected to propel high-end computing from its current status at the petascale level to its future at the exascale level, when machines will be capable of a thousand trillion calculations per second.

Constructed around many-core processors that utilise the venerable x86 instruction set, the Intel MIC architecture will prove more versatile and serviceable than architectures based on graphics processing units (GPUs). Users will be able to reuse their existing codes and programming knowledge, allowing for immediate scientific discovery and increased productivity. Further, users will be able to use standardised approaches and tools such as OpenMP and Intel Parallel Studio to optimise their codes to achieve high performance on both host processors and co-processors.