ISC11 announces keynote presentations

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The 26th International Supercomputing Conference, ISC’11, will feature four keynote presentations on an array of topics, from using supercomputers to simulate the human brain in order to (amongst others) explore hypotheses of mental diseases as well as treatments, to the European desire to be technologically independent and capable of exascale computing. These invited speakers have been recommended by 50 HPC experts from around the world. Their addresses are as follows:

Monday, 19 June: Henry Markram, project director of the Blue Brain Project at the École Polytechnique Fédérale de Lausanne, Switzerland. Markram will discuss ‘Simulating the Human Brain – The Next Decisive Years’. He will introduce the efforts to understand the brain and its diseases that produced a vast spectrum of data. The knowledge generated remains fragmented and daunting to synthesise; however, three progressions in scientific process suggest effective strategies to build on this work. The first is a revolution in the methods used to obtain data on the structure and function of the brain.

The second is the emergence of informatics-based science – the combined use of computers, mathematics and statistics to make sense of this data. The third is simulation-based research and its application to the life sciences. The Human Brain Project aims to embrace these three and build a facility capable of modelling and simulating the brain. As it develops, the facility will allow neuroscience and medical communities to exploit emerging information and computing technologies (ICT), while simultaneously driving transformations in ICT itself.

Tuesday, 20 June: Philippe Vannier, chairman and CEO of Bull, France. Vannier will discuss why access to high-performance computing resources is a key element in national competitiveness, both for the advancement of scientific research at the highest possible level, and to sustain economic growth through innovation. The USA, Japan, and now China are investing in their HPC industries, and Europe is recognising that its scientists and industry must have access to large-scale computing resources if they are to be competitive. Europe should also have the means to build a vast European HPC ecosystem to support innovation, because technological independence is more strategic than the availability of adequate computing resources, says Vannier.

In his talk ‘The Road to Exascale Computing – A European Challenge?’ Vannier will demonstrate that Europe can meet this challenge: Bull and CEA successfully co-designed Tera 100, the first European-developed system to break the Pflops barrier.

Wednesday, 21 June: Thomas Sterling, the Arnaud & Edwards Professor of Computer Science at Louisiana State University, USA. In his talk ‘HPC Achievement & Impact – 2011’, Sterling will review leaps in technologies, deployed systems, breakthrough computational accomplishments, and new methods and tools. New multicore chip architectures from major vendors, the building blocks of many of the prominent supercomputers worldwide, will be identified and described to track the growth and trends in performance opportunity. A number of the ground-breaking systems incorporating these and other key components will be characterised as new thresholds in sustained Pflops scale performance are achieved around the world.

Reflecting these advances will be computational science accomplishments exploiting these new capabilities and deployed resources. This presentation will user the perspective of new initiatives building towards the extremes of performance even to Eflops. It will conclude with the ‘Canonical HPC System’, a design point that represents the more widely-used components, sources, and scales over the preceding year.

Thursday, 22 June: Dean A. Klein, vice president of Memory System Development at Micron Technology. Klein states that memory, often viewed as a commodity component for computing platforms, is evolving into a role of prominence in today’s computing architecture. In part, the new role for memory is driven by a renewed focus on ‘the memory wall’, a real barrier to the continued performance gains of computing platforms. This focus is driving new architectures for both processors and for the DRAM that connects to them.

The second role of memory is being driven by the continued cost reduction of non-volatile memory, which is leading to its adoption as storage. NAND flash memory is today’s non-volatile memory of choice and is offered in multiple types, each with different characteristics. In his talk, ‘Future Trends in Memory Systems: Showstopper or Performance Potential for HPC?’, Klein will explore these evolving roles of memory, the challenges that exist around them, and the future of computing architectures built around these and future memories.

ISC’11 will be held in Hamburg, Germany, from 19 to 23 June 2011. Early bird registration begins on 1 March.