IBM to spend $3 billion researching new chip design

IBM has announced $3b research initiative to tackle the challenges of chip design for cloud and big data systems and search for solutions to a post-silicon future.

The research will be conducted over the next five years in two broad areas of early stage research. One area is aimed at current technology – designated ‘7 nanometer and beyond’ -- and focuses on silicon technology. The aim is to address the physical challenges that are impeding the scaling techniques used to create new semiconductors, reducing the manufacturer’s ability to produce the chips.

The second is focused on developing alternative technologies for post-silicon era chips using entirely different approaches, such as carbon nanotubes, or computational approaches such as neuromorphic or quantum computing.

Big data applications in particular are placing new challenges on system architecture, just as the underlying chip technology is reaching the limits of physical scaling. Bandwidth to memory, high speed communication and device power consumption are becoming increasingly challenging and critical.

The teams undertaking this research will consist of IBM Research scientists and engineers from Albany and Yorktown, New York; Almaden, California; and Europe.

Experts believe that semiconductors show promise to scale from today's 22 nanometers down to 14 and then 10 nanometers over the next few years. However, scaling to 7 nanometers and perhaps below, by the end of the decade will require significant investment and innovation in semiconductor architectures as well as invention of new tools and techniques for manufacturing.

‘The question is not if we will introduce 7 nanometer technology into manufacturing, but rather how, when, and at what cost?’ said John Kelly, senior vice president, IBM Research. ‘IBM engineers and scientists, along with our partners, are well suited for this challenge and are already working on the materials science and device engineering required to meet the demands of the emerging system requirements for cloud, big data, and cognitive systems. This new investment will ensure that we produce the necessary innovations to meet these challenges.’

Silicon transistors are approaching a point of physical limitation. Their increasingly small dimensions, now reaching the nanoscale, will reach the boundaries of materials science, as it stands today. Within a few more generations, classical scaling and shrinkage will no longer yield the sizable benefits of lower power, lower cost, and higher speed processors that the industry has become accustomed to.

Several exploratory research topics that could lead to major advancements in delivering dramatically smaller, faster and more powerful computer chips, including quantum computing, neurosynaptic computing, silicon photonics, carbon nanotubes, gallium arsenide, low power transistors and graphene.

IBM is continuing to invest in qubit based quantum computing science. A team at IBM Research recently demonstrated the first experimental realisation of parity check with three superconducting qubits, an essential building block for one type of quantum computer.

Neurosynaptic computing emulates the human brain's computing efficiency, size and power usage. IBM’s long-term goal is to build a neurosynaptic system with ten billion neurons and hundred trillion synapses, all while consuming only one kilowatt of power and occupying less than two litres in volume.

IBM has been involved in CMOS integrated silicon photonics for more than 12 years, a technology that integrates functions for optical communications on a silicon chip, and the IBM team has recently designed and fabricated the world's first monolithic silicon photonics based transceiver with wavelength division multiplexing.  Such transceivers will use light to transmit data between different components in a computing system at high data rates, low cost, and in an energy-efficient manner.

Carbon nanotubes are another area that IBM will focus its ‘7nm and beyond’ research. IBM recently demonstrated 2-way CMOS NAND gates using 50 nm gate length carbon nanotube transistors.

Carbon nanotube transistors can operate as excellent switches at molecular dimensions of less than ten nanometers – the equivalent to 10,000 times thinner than a strand of human hair and less than half the size of the leading silicon technology. Comprehensive modeling of the electronic circuits suggests that about a five to ten times improvement in performance compared to silicon circuits is possible.

Due to graphenes conductive properites and the fact that it is produced at only one atom thick make it applicable to faster switching transistors because  Electrons can move in graphene about ten times faster than in commonly used semiconductor materials such as silicon and silicon germanium. The technology is particularly applicable to applications in the handheld wireless communications business where it will be a more efficient switch than those currently used.  

Recently in 2013, IBM demonstrated the world's first graphene based integrated circuit receiver front end for wireless communications. The circuit consisted of a 2-stage amplifier and a down converter operating at 4.3 GHz. 

The company will continue to fund and collaborate with university researchers to explore and develop the future technologies for the semiconductor industry. In particular, it will continue to support and fund university research through private-public partnerships such as the NanoElectornics Research Initiative (NRI), and the Semiconductor Advanced Research Network (STARnet), and the Global Research Consortium (GRC) of the Semiconductor Research Corporation.

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