Semtech, a supplier of analogue and mixed-signal semiconductors, has used Matlab and Simulink to reduced development time of optimised digital receivers in wireless RF devices. Semtech used the MathWorks tools to create FPGA prototypes 50 per cent faster than before, reduce verification time from weeks to days and shorten development time by 33 per cent.
A Simulink model based on system specifications helped engineers rapidly evaluate design ideas and improved collaboration among engineering teams. Simulink and Simulink HDL Coder enabled engineers to create prototypes in a few weeks and eliminate hand-coding. Using EDA Simulator Link, Semtech engineers reused the Simulink system model to test multiple critical points in the design, verify the VHDL in less than a day, and reduce overall verification time from weeks to days.
'We were tasked with the challenges of accelerating the development time for a digital receiver and finding a way to improve our development workflow. MathWorks tools enabled us to explore more alternatives and new features, and ultimately deliver a more optimised, better performing design,' said Frantz Prianon, IC design engineer at Semtech. 'With Simulink and Simulink HDL Coder, once we have simulated the model we can generate VHDL directly, prototype on an FPGA, and fully verify the VHDL implementation. It saves a lot of time, and the generated code contains some optimisations we hadn’t thought of.'
