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Automatic HDL generation reduces thermal imaging FPGA development time

Flir Systems has reduced its thermal imaging FPGA development time from concept to field-testable prototype by 60 per cent through Matlab and HDL Coder. The company was able to speed development, complete enhancements in hours instead of weeks and reuse code for prototyping and production by using Matlab to design, simulate and evaluate algorithms, and HDL Coder to rapidly implement the best algorithms on FPGAs.

Flir’s algorithm engineers produce FPGA prototypes themselves instead of handing written specifications to hardware engineers, who may not have full knowledge of the algorithm. This new thermal imaging algorithm development workflow also eliminates the error-prone step of translating algorithms to HDL by hand, adding time for developers to try more design iterations.


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