RASS - Reconfigurable Accelerating Scalable SuperComputing
6 August 2008
Sundance has introduced RASS, an adaptable supercomputing accelerator platform supported by commercially available industry standard design tools. The RASS has been created to easily integrate with existing HPC infrastructure and is supported by a widely available and mature design ecosystem.
Designed to integrate with industry standard processors and computing infrastructure, the RASS features a modular, interchangeable array of high performance FPGAs and GPUs to deliver high performance, low latency and flexibility across single precision and double precision computation applications. By exploiting parallel processing techniques and modular design, the RASS delivers a small footprint, energy efficient, high density solution to applications in the capital markets, life sciences, national laboratories and computational fluid dynamics (CFD)
At the heart of RASS are banks of tightly coupled Xilinx Virtex 5 FPGAs that include 640 Xilinx XtremeDSP slices capable of delivering up to 352 GMACs of performance. Sitting on a carrier, multiple FPGAs can be connected via a Rocket Serial Link (RSL) I/O interface and the architecture is adaptable to different applications and computation demands. More than 20 different daughter card and processing fabric combinations available.
The SMT148-FX carrier offers SATA, USB 2.0, FireWire, Gigabit Ethernet, RS485, RS232, LVDS interfaces. It also contains a Virtex-4 FX60 FPGA that includes two PowerPC cores that can be used as interface controllers, leaving the FPGAs free for extreme coprocessor acceleration.
The massively parallel processing capabilities of RASS significantly lower energy consumption to yield lower cooling costs and a lower cooling BOM. It delivers a market leading performance per watt and its small footprint enables significant real estate savings in space constrained data centres.
To mitigate the learning curve and risk of reliance upon proprietary tools and languages, the RASS platform is supported by widely available industry standard design tools and languages. Design support from the The MathWorks , Xilinx, 3L Diamond, Impulse, HDL and C/C++ providers offers a readily available and integrated development environment. The design ecosystem enables immediate access to libraries of intellectual property including Navier-Stokes, Black-Scholes, LINPACK, Monte Carlo and Amber,